PCIe Gen 6, PAM4 & the Need for High Speed
Join Electro Rent and our featured presenters for a live webinar discussing test challenges and test solutions for today’s high-speed environments. This two-part series will be led by top application engineers from Anritsu and Tektronix. Simply complete the registration form on this page and you will reserve seats to both events.
Tuesday, May 24, 2022
(Part 1 of 2 with Anritsu)
PAM4 BER & JTOL Test Solutions for PCIe 6 & Beyond with Anritsu
This session will provide an overview of 32 Gbaud and above PAM4 BER test and Jitter tolerance test. It will also include Forward Error Correction (FEC) and burst errors analysis. Who should attend: Engineers working on PCIe 6.0 or 400/800GE applications.
Key Topics:
- Complete PAM4 solution consisting of Anritsu BERT and Tektronix
- PAM4 BERT Product Overview & Capabilities
- PAM4 BER & Jitter Tolerance Test
- FEC Burst Error Capture & Analysis
Tuesday, June 7, 2022
(Part 2 of 2 with Tektronix)
What’s New in PCI Express 6.0 Specification and Physical Layer Testing Challenges with Tektronix
Key Topics:
- Complete PAM4 solution consisting of Anritsu BERT and Tektronix
- PCIe 6.0 specification updates
- 64 GT/s PAM4 Base transmitter measurements
- Measurement challenges for reference clock jitter, receiver calibration, and JTOL
BROUGHT TO YOU BY
Speakers
Hiroshi Goto, Senior Market Development Manager, Anritsu
Hiroshi Goto has over 25 years of experience as a high speed and optical Engineer at Anritsu Company holding a variety of positions, including Design Engineer, Product Marketing Engineer and currently high speed and optical Product Manager and Business Development Manager. Mr. Goto holds a Bachelor’s degree in Physics from Aoyama Gakuin University. He resides in the Dallas area and has authored numerous industry application notes and white papers and frequently speaks on the topic of signal integrity.
Joey Chiu, PCIe Applications Engineer, Tektronix
Joey Chiu is the PCIe Applications Engineer for Tektronix. Joey is a technology enthusiast and a passionate programmer, with a focus on automated test for high-speed serial standards. He brings a decade of experience to his current role where he has created several custom solutions for PCIe and related standards. Previously he was working on RF and mixed-signal applications. Joey received both his Master’s and Bachelor’s degrees in Mechanical Engineering from National Taiwan University.
Overview
Title: PCIe Gen 6, PAM4 & the Need for High Speed (Parts 1 & 2)
Date: Tuesday, May 24, 2022 (Part 1 with Anritsu)
Tuesday, June 7, 2022 (Part 2 with Tektronix)
Time: 10:00 AM Pacific Daylight Time
Duration: 30 Minutes + Q & A